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1 ltc1658 14-bit rail-to-rail micropower dac in msop features n 14-bit resolution n 8-lead msop package n buffered true rail-to-rail voltage output n 3v or 5v single supply operation n very low power: i cc(typ) = 270 m a n power-on reset n 3-wire cascadable serial interface is compatible with spi and microwire tm n maximum dnl error: 1lsb n low cost the ltc ? 1658 is a single supply, rail-to-rail voltage out- put, 14-bit digital-to-analog converter (dac) in an 8-lead msop package. it includes an output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. the ltc1658 output swings from 0v to v ref . the ref pin can be tied to v cc for rail-to-rail output swing. the ltc1658 operates from a single 2.7v to 5.5v supply. the typical power supply current is 270 m a. the low power supply current makes the ltc1658 ideal for battery-powered applications. the space saving msop provides the smallest 14-bit dac system available. descriptio n u functional block diagram: 14-bit rail-to-rail dac n digital calibration n industrial process control n automatic test equipment n cellular telephones applicatio n s u , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u + 14-bit dac 2.7v to 5.5v gnd power-on reset to other dacs 16-bit shift reg and dac latch m p d in v cc 14 ref 2 86 d out 4 5 1658 ta01 clk 1 cs/ld 3 7 rail-to-rail voltage output v out microwire is a trademark of national semiconductor corporation. code 0 1.0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 1.0 dnl error (lsb) 4096 8192 1658 ta02 12288 16383 differential nonlinearity vs input code
2 ltc1658 absolute m axi m u m ratings w ww u v cc to gnd .............................................. C 0.5v to 7.5v ttl input voltage .................................... C 0.5v to 7.5v v ref .......................................................... C 0.5v to 7.5v v out ........................................... C 0.5v to (v cc + 0.5v) junction temperature .......................... C 65 c to 125 c operating temperature range commercial ............................................ 0 c to 70 c industrial ............................................. C40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c v cc = 2.7v to 5.5v, v out unloaded, ref v cc , t a = t min to t max , unless otherwise noted. electrical characteristics order part number order part number ltc1658cms8 ltc1658ims8 s8 part marking 1658 1658i ltc1658cn8 ltc1658in8 ltc1658cs8 ltc1658is8 consult factory for military grade parts. t jmax = 125 c, q ja = 100 c/w(n8) t jmax = 125 c, q ja = 150 c/w(s8) 1 2 3 4 8 7 6 5 top view clk d in cs/ld d out v cc v out ref gnd n8 package 8-lead pdip s8 package 8-lead plastic so t jmax = 150 c, q ja = 250 c/w 1 2 3 4 clk d in cs/ld d out 8 7 6 5 v cc v out ref gnd top view ms8 package 8-lead plastic msop ms8 part marking ltcw ltfw wu u package / o rder i for atio (note 1) symbol parameter conditions min typ max units dac resolution l 14 bits monotonicity l 14 bits dnl differential nonlinearity v ref v cc C 0.1v (note 2) l 1.0 lsb inl integral nonlinearity v ref v cc C 0.1v (note 2) l 8.0 lsb zero scale error t a = 25 c, n8 and s8 package 1.5 mv t a = t min to t max , n8 and s8 package l 4.0 mv t a = t min to t max , msop package l 7.0 mv offset error t a = 25 c, n8 and s8 package, (note 7) 1.5 mv t a = t min to t max , n8 and s8 package, (note 7) l 4.0 mv t a = t min to t max , msop package, (note 7) l 7.0 mv v os tc offset error temperature 5 m v/ c coefficient gain error l 20 lsb gain error drift 2.5 ppm/ c power supply v cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current 2.7v v cc 5.5v (note 4) l 270 550 m a op amp dc performance short-circuit current low v out shorted to gnd l 55 120 ma short-circuit current high v out shorted to v cc l 55 120 ma
3 ltc1658 v cc = 2.7v to 5.5v, v out unloaded, ref v cc , t a = t min to t max , unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units output impedance to gnd input code = 0 l 70 200 w output line regulation input code = 16383, v cc = 2.7v to 5.5v, ref = 2.5v l 1.5 mv/v ac performance voltage output slew rate l 0.35 1.0 v/ m s voltage output settling time (note 3) to 0.5lsb 12 m s digital feedthrough 0.3 nv ? s reference input r in ref input resistance l 30 60 k w v ref ref input range (notes 5, 6) l 0v cc v digital i/o v ih digital input high voltage v cc = 5v l 2.4 v v il digital input low voltage v cc = 5v l 0.8 v v oh digital output high voltage v cc = 5v, i out = C 1ma, d out only l v cc C 0.7 v v ol digital output low voltage v cc = 5v, i out = 1ma, d out only l 0.4 v v ih digital input high voltage v cc = 3v l 2.0 v v il digital input low voltage v cc = 3v l 0.6 v v oh digital output high voltage v cc = 3v, i out = C 1ma, d out only l v cc C 0.7 v v ol digital output low voltage v cc = 3v, i out = 1ma, d out only l 0.4 v i leak digital input leakage v in = gnd to v cc l 10 m a c in digital input capacitance (note 6) l 10 pf switching (v cc = 4.5v to 5.5v) t 1 d in valid to clk setup l 40 ns t 2 d in valid to clk hold l 0ns t 3 clk high time (note 6) l 40 ns t 4 clk low time (note 6) l 40 ns t 5 cs/ld pulse width (note 6) l 50 ns t 6 lsb clk to cs/ld (note 6) l 40 ns t 7 cs/ld low to clk (note 6) l 20 ns t 8 d out output delay c load = 15pf l 5 100 ns t 9 clk low to cs/ld low (note 6) l 20 ns switching (v cc = 2.7v to 5.5v) t 1 d in valid to clk setup l 60 ns t 2 d in valid to clk hold l 0ns t 3 clk high time (note 6) l 60 ns t 4 clk low time (note 6) l 60 ns t 5 cs/ld pulse width (note 6) l 80 ns t 6 lsb clk to cs/ld (note 6) l 60 ns t 7 cs/ld low to clk (note 6) l 30 ns t 8 d out output delay c load = 15pf l 10 150 ns t 9 clk low to cs/ld low (note 6) l 30 ns
4 ltc1658 electrical characteristics the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life a device may be impaired. note 2: nonlinearity is defined from code 50 to code 16383 (full scale). see applications information. note 3: dac switched between code 16383 and code 50. note 4: digital inputs at 0v or v cc . note 5: v out can only swing from (gnd + ? v os ? ) to (v cc C ? v os ? ) when output is unloaded. see applications information. note 6: guaranteed by design. not subject to test. note 7: measured at code 50. typical perfor a ce characteristics uw differential nonlinearity (dnl) vs input code supply current vs logic input voltage code 0 ? ? ? ? ? 0 1 2 3 4 5 inl error (lsb) 4096 8192 1658 g01 12288 16383 integral nonlinearity (inl) vs input code logic input voltage (v) 012345 supply current (ma) 1658 g03 3 2 1 0 all digital inputs tied together code 0 1.0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8 1.0 dnl error (lsb) 4096 8192 1658 g02 12288 16383 minimum output voltage vs output sink current offset error vs temperature minimum supply headroom for full output swing vs load current output sink current (ma) 0 5 10 15 output pull-down voltage (v) 1658 g05 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 code: all zeros 125 c 25 c ?5 c load current (ma) 0 5 10 15 v cc ?v out (v) 1658 g04 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ? v out < 1lsb code: all 1s v out = 4.096v 125 c 25 c ?5 c temperature ( c) ?5 ?5 5 35 65 95 125 offset error (lsb) 1658 g06 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5 ltc1658 typical perfor a ce characteristics uw broadband noise temperature ( c) ?5 ?5 5 35 65 95 125 gain error (lsb) 1658 g06 5 4 3 2 1 0 ? ? ? ? ? gain error vs temperature bw = 1hz to 200 m s/div 1658 g08 100khz pi n fu n ctio n s uuu clk (pin 1): the ttl level input for the serial interface clock. d in (pin 2): the ttl level input for the serial interface data. data on the d in pin is latched into the shift register on the rising edge of the serial clock and is loaded msb first. the ltc1658 requires a 16-bit word to be loaded in. the last two bits are dont cares. cs/ld (pin 3): the ttl level input for the serial inter- face enable and load control. when cs/ld is low the clk signal is enabled, so the data can be clocked in. when cs/ld is pulled high, data is loaded from the shift register into the dac register, updating the dac output. d out (pin 4): output of the shift register which becomes valid on the rising edge of the serial clock. gnd (pin 5): ground. ref (pin 6): reference input. there is a gain of one from this pin to the output. when tied to v cc the output will swing from gnd to v cc . the output can only swing to within its offset specification of v cc (see applicatons information). v out (pin 7): buffered rail-to-rail dac output. v cc (pin 8): positive supply input. 2.7v v cc 5.5v. 1lsb/div
6 ltc1658 ti i g diagra wu w b12 b13 msb t 1 t 6 t 9 bx dummy bx dummy b0 lsb b11 t 7 t 2 t 4 t 3 t 8 clk d in d out cs/ld t 5 1658 td b13 previous word b13 current word b11 b12 bx bx defi itio s uu differential nonlinearity (dnl): the difference between the measured change and the ideal 1lsb change for any two adjacent codes. the dnl error between any two codes is calculated as follows: dnl = ( d v out C lsb)/lsb where d v out is the measured voltage difference between two adjacent codes. digital feedthrough: the glitch that appears at the analog output caused by ac coupling from the digital inputs when they change state. the area of the glitch is specified in (nv)(sec). gain error: gain error is the difference between the output of a dac from its ideal full-scale value after offset error has been adjusted. integral nonlinearity (inl): the deviation from a straight line passing through the endpoints of the dac transfer curve (endpoint inl). because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. the inl error at a given input code is calculated as follows: inl = [v out C v os C (v fs C v os )(code/16383)]/lsb where v out is the output voltage of the dac measured at the given input code. least significant bit (lsb): the ideal voltage difference between two successive codes. lsb = v ref /16384 resolution (n): defines the number of dac output states (2 n ) that divide the full-scale range. resolution does not imply linearity. voltage offset error (v os ): nominally, the voltage at the output when the dac is loaded with all zeros. a single supply dac can have a true negative offset, but the output cannot go below zero (see applications information). for this reason, single supply dac offset is measured at the lowest code that guarantees the output will be greater than zero.
7 ltc1658 operatio u serial interface the data on the d in input is loaded into the shift register on the rising edge of the clock. the msb is loaded first. the dac register loads the data from the shift register when cs/ld is pulled high. the clock is disabled internally when cs/ld is high. note: clk must be low before cs/ld is pulled low to avoid an extra internal clock pulse. the input word must be 16 bits wide. the last two bits are dont cares. the buffered output of the 16-bit shift register is available on the d out pin which swings from gnd to v cc . multiple ltc1658s may be daisy-chained together by connecting the d out pin to the d in pin of the next chip while the clock and cs/ld signals remain common to all chips in the daisy chain. the serial data is clocked to all of the chips then the cs/ld signal is pulled high to update all of them simultaneously. voltage output the ltc1658 rail-to-rail buffered output can source or sink 5ma over the entire operating temperature range while pulling to within 400mv of the positive supply voltage or ground. the output swings to within a few millivolts of ei- ther supply rail when unloaded and has an equivalent out- put resistance of 40 w , at 5v v cc , when driving a load to the rails. the output can drive 1000pf without going into os- cillation. the output swings from 0v to the voltage at the ref pin, i.e., there is a gain of 1 from ref to v out . please note, if ref is tied to v cc the output can only swing to (v cc C v os ). see applications information.
8 ltc1658 rail-to-rail output considerations in any rail-to-rail dac, the output swing is limited to voltages within the supply range. if the dac offset is negative, the output for the lowest codes limits at 0v as shown in figure 1b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 1c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur. applicatio n s i n for m atio n wu u u figure 1. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for input codes near full scale when v ref = v cc 1658 f01 input code (b) output voltage negative offset 0v 8192 0 16383 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse
9 ltc1658 an optoisolated 4ma to 20ma process controller clk d in cs/ld 1 f in out q1 2n3440 r s 10 i out v loop 3.8v to 30v v cc ref v out from opto- isolated inputs ltc1658 1658 ta04 lt 1121-3.3 3.01k 1% + + lt1077 1k 20k 237k 1% 5k 60.4k 1% optoisolators 500 3.3v 3.6k 4n28 clk d in cs/ld clk d in cs/ld this circuit shows how to use an ltc1658 to make an optoisolated digitally controlled 4ma to 20ma process controller. the controller circuitry, including the optoisolation, is powered by the loop voltage that can have a wide range of 3.8v to 30v. the 3.3v output of the lt1121-3.3 is used for the 4ma offset current and v out is used for the digitally controlled 0ma to 16ma current. r s is a sense resistor and the op amp modulates the transis- tor q1 to provide the 4ma to 20ma current through this resistor. the potentiometers allow for offset and full-scale adjustment. the control circuitry dissipates well under the 4ma budget at zero-scale. typical applicatio s u
10 ltc1658 a 14-bit analog input/output channel for a pc d out 10 11 1 2 3 4 8 7 6 5 v cc v out ref gnd clk d in cs/ld d out u2 ltc1658 analog output 2 4 3 5 1 6 q clr q d pr ck u3 1/2 74hc74 5v 5v 3 select tx rts dtr cts 41 2 6 2 4 u4 lt1021-5 12 10 11 9 13 8 q clr q d pr ck u3 1/2 74hc74 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc v ss busy convst rd shdn dgnd d out a in + a in ? v ref v refcomp agnd extclkin sclk clkout u1 ltc1417 510 510 510 510 10 f 1 f 1 f d1 differential input d2 d6 d5 d3 d4 1 f 51k 9 d in 85 6 51k sclk 13 12 51k c4 150 f c3 0.1 f 5v c5 47 f 1658 ta05 1658 ta05 5v typical applicatio s u
11 ltc1658 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) msop (ms8) 1197 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) typ 12 3 4 0.192 0.004 (4.88 0.10) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102)
12 ltc1658 ? linear technology corporation 1998 1658f lt/tp 0299 4k ? printed in usa typical applicatio n u 14-bit, 3v to 5v single supply, voltage output dac d in clk cs/ld d out p 0.1 m f output 0v to ref v cc ref v out gnd ltc1658 to next dac for daisy-chaining 2.7v to 5.5v 1658 ta03 related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments ltc1257 single 12-bit v out dac, full scale: 2.048v, v cc : 4.75v to 15.75v, 5v to 15v single supply, complete v out dac in reference can be overdriven up to 12v, i.e., fs max = 12v so-8 package ltc1446/ltc1446l dual 12-bit v out dacs in so-8 package ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1448 dual 12-bit v out dac, v cc : 2.7v to 5.5v output swings from gnd to ref. ref input can be tied to v cc ltc1450/ltc1450l single 12-bit v out dacs with parallel interface ltc1450: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1450l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1451 single rail-to-rail 12-bit dac, full scale: 4.095v, v cc : 4.5v to 5.5v, 5v, low power complete v out dac in so-8 package internal 2.048v reference brought out to pin ltc1452 single rail-to-rail 12-bit v out multiplying dac, v cc : 2.7v to 5.5v low power, multiplying v out dac with rail-to-rail buffer amplifier in so-8 package ltc1453 single rail-to-rail 12-bit v out dac, full scale: 2.5v, v cc : 2.7v to 5.5v 3v, low power, complete v out dac in so-8 package ltc1454/ltc1454l dual 12-bit v out dacs in so-16 package with added functionality ltc1454: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1454l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1456 single rail-to-rail output 12-bit dac with clear pin, low power, complete v out dac in so-8 full scale: 4.095v, v cc : 4.5v to 5.5v package with clear pin ltc1458/ltc1458l quad 12 bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1659 single rail-to-rail 12-bit v out dac in 8-pin msop, v cc : 2.7v to 5.5v low power, multiplying v out dac in ms8 package. output swings from gnd to ref. ref input can be tied to v cc . references lt1019 precision voltage reference ultralow drift 5ppm/ c, initial accuracy: 0.05% lt1634 micropower precision reference low drift 10ppm/ c, initial accuracy: 0.05%

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